In existing display devices, a gate line is usually provided with a scan signal by a gate driving circuit. The gate driving circuit includes a shift register which is formed by cascading a plurality of shift register cells. Generally, a shift register cell is driven by a clock signal having two or more phases, which increases the complexity of the shift register cell and is unfavorable to a narrow-bezel design of the display device.
Therefore, how to simplify the shift register cell becomes a technical problem to be solved in the art.